W3EG7218S262AD4资料

White Electronic DesignsW3EG7218S-AD4

-BD4

PRELIMINARY*

128MB – 16Mx72 DDR SDRAM UNBUFFERED w/PLL

FEATURES

󰀂 Double-data-rate architecture󰀂 DDR200 and DDR266

󰀂 Bi-directional data strobes (DQS)󰀂 Differential clock inputs (CK & CK#)󰀂 Programmable Read Latency 2,2,5 (clock)󰀂 Programmable Burst Length (2,4,8)

󰀂 Programmable Burst type (sequential & interleave) 󰀂 Edge aligned data output, center aligned data input󰀂 Auto and self refresh󰀂 Serial presence detect󰀂 Power Supply: 2.5V ± 0.20V

󰀂 JEDEC standard 200 pin SO-DIMM package

•

Package height options: AD4: 35.5mm (1.38\") and BD4: 31.75mm (1.25\")

* This product is under development, is not qualifi ed or characterized and is subject to change without notice.

DESCRIPTION

The W3EG7218S is a 16Mx72 Double Data Rate SDRAM memory module based on 128Mb DDR SDRAM component. The module consists of nine 16Mx8 DDR SDRAMs in 66 pin TSOP package mounted on a 200 Pin FR4 substrate.

Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lenths allow the

same device to be useful for a variety of high bandwidth, high performance memory system applications.

OPERATING FREQUENCIES

DDR266 @CL=2

Clock SpeedCL-tRCD-tRP

133MHz2-2-2

DDR266 @CL=2.5

133MHz2.5-3-3

DDR200 @CL=2

100MHz2-2-2

November 2004Rev. 1

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White Electronic DesignsPIN CONFIGURATION

Pin123456710111213141516171819202122232425262728293031323334353637383940414243444547484950

SymbolVREFVREFVSSVSSDQ0DQ4DQ1DQ5VCCVCCDQS0DQM0DQ2DQ6VSSVSSDQ3DQ7DQ8DQ12VCCVCCDQ9DQ13DQS1DQM1VSSVSSDQ10DQ14DQ11DQ15VCCVCCCK0VCCCK0#VSSVSSVSSDQ16DQ20DQ17DQ21VCCVCCDQS2DQM2DQ18DQ22

Pin515253545556575859606162636566676869707172737475767778798081828384858687809192939495969799100

SymbolVSSVSSDQ19DQ23DQ24DQ28VCCVCCDQ25DQ29DQS3DQM3VSSVSSDQ26DQ30DQ27DQ31VCCVCCCB0CB4CB1CB5VSSVSSDQS8DQM8CB2CB6VCCVCCCB3CB7NCNCVSSVSSNCVSSNCVCCVCCVCCNCCKE0NCNCNCA11

Pin101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150

SymbolA9ABVSSVSSA7A6A5A4A3A2A1A0VCCVCCA10/APBA1RA0RAS#WE#CAS#CS0NCNCNCVSSVSSDQ32DQ36DQ33DQ37VCCVCCDQS4DQM4DQ34DQ38VSSVSSDQ35DQ39DQ40DQ44VCCVCCDQ41DQ45DQS5DQM5VSSVSS

Pin15115215315415515615715815916016116216311651661671681691701711721731741751761771781791801811821831841851861871881190191192193194195196197198199200

SymbolDQ42DQ46DQ43DQ47VCCVCCVCCNCVSSNCVSSVSSDQ48DQ52DQ49DQ53VCCVCCDQS6DQM6DQ50DQ54VSSVSSDQ51DQ55DQ56DQ60VCCVCCDQ57DQ61DQS7DQM7VSSVSSDQ58DQ62DQ59DQ63VCCVCCSDASA0SCLSA1VCCSPDSA2VCCIDNC

A0-A11BA0-BA1DQ0-DQ63CB0-CB7DQS0-DQS8CK0CK0#CKE0CS0#RAS#CAS#WE#VCCVCCQVSSVREFVCCSPDSDASCLSA0-SA2VCCIDNC

W3EG7218S-AD4

-BD4

PRELIMINARY

PIN NAMES

Address input (Multiplexed)Bank Select AddressData Input/OutputCheck bits

Data Strobe Input/OutputClock InputClock InputClock Enable InputChip Select InputRow Address StrobeColumn Address StrobeWrite EnablePower Supply (2.5V)Power Supply for DQS (2.5V)Ground

Power Supply for ReferenceSerial EEPROM Power Supply (2.3V to 3.6V)Serial Data I/OSerial Clock

Address in EEPROMVCC Identifi cation FlagNo Connect

DQM0-DQM8Data-In Mask

November 2004

Rev. 1

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White Electronic DesignsFUNCTIONAL BLOCK DIAGRAM

CS0#DQS0DQM0DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQS1DQM1DQ8DQ9DQ10DQ11DQ12DQ13DQ14DQ15DQS2DQM2DQ16DQ17DQ18DQ19DQ20DQ21DQ22DQ23DQS3DQM3DQ24DQ25DQ26DQ27DQ28DQ29DQ30DQ31DQS8DQM8CB0CB1CB2CB3CB4CB5CB6CB7 DM CS# DQSDQDQDQDQDQDQDQDQCK0CK0#120PLL DM CS# DQSDQDQDQDQDQDQDQDQ DM CS# DQSDQDQDQDQDQDQDQDQDQS7DQM7DQ56DQ57DQ58DQ59DQ60DQ61DQ62DQ63 DM CS# DQSDQDQDQDQDQDQDQDQ DM CS# DQSDQDQDQDQDQDQDQDQDQS6DQM6DQ48DQ49DQ50DQ51DQ52DQ53DQ54DQ55 DM CS# DQSDQDQDQDQDQDQDQDQ DM CS# DQSDQDQDQDQDQDQDQDQDQS5DQM5DQ40DQ41DQ42DQ43DQ44DQ45DQ46DQ47 DM CS# DQSDQDQDQDQDQDQDQDQDQS4DQM4DQ32DQ33DQ34DQ35DQ36DQ37DQ38DQ39 DM CS# DQSDQDQDQDQDQDQDQDQW3EG7218S-AD4

-BD4

PRELIMINARY

DDR SDRAM X 2DDR SDRAM X 2DDR SDRAM X 2DDR SDRAM X 2DDR SDRAM X 1SERIAL PDSCLWPA0A1A2SDABA0, BA1A0-A11RAS#CAS#CKE0WE#BA0, BA1A0-A11RAS#CAS#CKE0WE#VDDSPDVDDVREFVSSSA0SA1SA2SPD/EEPROMDDR SDRAMS DDR SDRAMS DDR SDRAMS Note: All resistor values are 22Ω unless otherwise indicatedNovember 2004Rev. 1

3

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White Electronic DesignsABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to VSSVoltage on VCC supply relative to VSSStorage TemperaturePower DissipationShort Circuit Current

Note:

Permanent device damage may occur if \"ABSOLUTE MAXIMUM RATINGS\" are exceeded.Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

W3EG7218S-AD4

-BD4

PRELIMINARY

SymbolVIN, VOUTVCC, VCCQTSTGPDIOS

Value– 0.5 ~ 3.6–1.0 ~ 3.6– 55 ~ +150

950

UnitsVV°CWmA

DC CHARACTERISTICS

0°C ≤ TA ≤ 70°C, VCC = 2.5V ± 0.2V

ParameterSupply VoltageSupply VoltageReference VoltageTermination VoltageInput High VoltageInput Low VoltageOutput High Voltage Output Low Voltage

SymbolVCCVCCQVREFVTTVIHVILVOHVOL

Min2.32.31.151.15VREF + 0.15– 0.3VTT+ 0.76—

Max2.72.71.351.35VCCQ + 0.3VREF – 0.15

—VTT – 0.76

UnitVVVVVVVV

CAPACITANCE

TA = 25°C, f = 1MHz, VCC = 2.5V

Parameter

Input Capacitance (A0-A11)Input Capacitance (RAS#,CAS#,WE#)Input Capacitance (CKE0,CKE1)Input Capacitance (CK0,CK0#)Input Capacitance (CS0#,CS1#)Input Capacitance (DQM0-DQM8)Input Capacitance (BA0-BA1)

Data input/output Capacitance (DQ0-DQ63)(DQS)Data input/output Capacitance (CB0-CB7)

SymbolCIN1CIN2CIN3CIN4CIN5CIN6CIN7COUTCOUT

Max2929295.52982988

UnitpFpFpFpFpFpFpFpFpF

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White Electronic DesignsIDD SPECIFICATIONS AND TEST CONDITIONS

W3EG7218S-AD4

-BD4

PRELIMINARY

(Recommended operating conditions, 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V)

DDR266 @CL=2

ParameterOperating Current

SymbolConditionsIDD0

One device bank; Active - Precharge; (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. tRC=tRC(MIN); tCK=tCKOne device bank; Active-Read-Precharge; Burst = 2;

tRC=tRC(MIN);tCK=tCK (MIN); Iout = 0mA; Address and control inputs changing once per clock cycle.

All device banks idle; Power-down mode; tCK=tCK(MIN); CKE=(low)

CS# = High; All device banks idle; tCK=tCK(MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM.

One device bank active; Power-down mode; tCK(MIN); CKE=(low)

CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS(MAX); tCK=tCK(MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle.

Burst = 2; Reads; Continous burst; One device bank

active;Address andcontrol inputs changing once per clock cycle; tCK=tCK(MIN); IOUT = 0mA.

Burst = 2; Writes; Continous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK(MIN); DQ,DM and DQS inputs changing twice per clock cycle.tRC=tRC(MIN)CKE ≤ 0.2V

Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK(MIN); Address and control inputs change only during Active Read or Write commands

Max1125

DDR266 @CL=2.5Max990

DDR200 @CL=2Max990

UnitsmA

Operating CurrentIDD1121510801080mA

Precharge Power-Down Standby CurrentIdle Standby Current

IDD2PIDD2F

27405

27405

27405

mAmA

Active Power-Down Standby CurrentActive Standby Current

IDD3PIDD3N

225450

225450

225450

mAmA

Operating CurrentIDD4R126011701170mA

Operating CurrentIDD4W126011251125mA

Auto Refresh CurrentSelf Refresh CurrentOperating Current

IDD5IDD6IDD7A

2385273195

1980272970

1980272970

mAmAmA

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White Electronic DesignsDETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A

IDD1 : OPERATING CURRENT : ONE BANK

1. Typical Case : VCC=2.5V, T=25°C2. Worst Case : VCC=2.7V, T=10°C

3. Only one bank is accessed with tRC (min), Burst

Mode, Address and Control inputs on NOP edge are changing once per clock cycle. IOUT = 0mA4. Timing Patterns :

•

DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,

BL=4, tRCD=2*tCK, tRAS=5*tCK

Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst

DDR266 (133MHz, CL=2.5) : tCK=7.5ns,

CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCKRead : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address

changing; 50% of data changing at every burstDDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK

Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address

changing; 50% of data changing at every burst

W3EG7218S-AD4

-BD4

PRELIMINARY

IDD7A : OPERATING CURRENT : FOUR BANKS

1. Typical Case : VCC=2.5V, T=25°C2. Worst Case : VCC=2.7V, T=10°C

3. Four banks are being interleaved with tRC (min),

Burst Mode, Address and Control inputs on NOP edge are not changing. Iout=0mA4. Timing Patterns :

•

DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,

BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with Autoprecharge

Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst

DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCKRead with Autoprecharge

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst

DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2, BL=4, tRRD=2*tCK, tRCD=2*tCK

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst

•

•

•

•

Legend : A = Activate, R = Read, W = Write, P = Precharge, N = NOPA (0-3) = Activate Bank 0-3R (0-3) = Read Bank 0-3

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White Electronic DesignsW3EG7218S-AD4

-BD4

PRELIMINARY

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

AC CHARACTERISTICSPARAMETER

Access window of DQs from CK/CK#CK high-level widthCK low-level widthClock cycle time

DQ and DM input hold time relative to DQSDQ and DM input setup time relative to DQSDQ and DM input pulse width (for each input)Access window of DQS from CK/CK#DQS input high pulse widthDQS input low pulse width

DQS-DQ skew, DQS to last DQ valid, per group, per accessWrite command to fi rst DQS latching transitionDQS falling edge to CK rising - setup timeDQS falling edge from CK rising - hold timeHalf clock period

Data-out high-impedance window from CK/CK#Data-out low-impedance window from CK/CK#Address and control input hold time (slow slew rate)Address and control input setup time (slow slew rate)Address and Control input pulse width (for each input)LOAD MODE REGISTER command cycle time

CL = 2.5CL = 2

SYMBOLtACtCHtCLtCK (2.5)tCK (2)tDHtDStDIPWtDQSCKtDQSHtDQSLtDQSQtDQSStDSStDSHtHPtHZtLZtIHStISStIPWtMRD

-0.750.900.902.2150.750.20.2

tCH, tCL

+0.75

-0.751.11.12.215

MIN-0.750.450.457.57.50.50.51.75-0.600.350.35

0.51.25

0.750.20.2

tCH, tCL

+0.75

+0.75262

MAX+0.750.550.551313

MIN-0.750.450.457.5100.50.51.75-0.750.350.35

0.61.25+0.75265/202

MAX+0.750.550.551313

UNITSnstCKtCKnsnsnsnsnsnstCKtCKnstCKtCKtCKnsnsnsnsnsnsns

3016, 3716, 37121222, 232620, 4540, 4523, 2723, 2727NOTES

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White Electronic DesignsW3EG7218S-AD4

-BD4

PRELIMINARY

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (continued)

AC CHARACTERISTICSPARAMETER

DQ-DQS hold, DQS to fi rst DQ to go non-valid, per accessData Hold Skew Factor

ACTIVE to PRECHARGE command

ACTIVE to READ with Auto precharge commandACTIVE to ACTIVE/AUTO REFRESH command periodAUTO REFRESH command periodACTIVE to READ or WRITE delayPRECHARGE command periodDQS read preambleDQS read postamble

ACTIVE bank a to ACTIVE bank b commandDQS write preamble

DQS write preamble setup timeDQS write postambleWrite recovery time

Internal WRITE to READ command delayData valid output window (DVW)REFRESH to REFRESH command intervalAverage periodic refresh intervalTerminating voltage delay to VDD

Exit SELF REFRESH to non-READ commandExit SELF REFRESH to READ command

SYMBOLtQHtQHStRAStRAPtRCtRFCtRCDtRPtRPREtRPSTtRRDtWPREtWPREStWPSTtWRtWTR

na

262MINtHP - tQHS

0.75

4015607515150.90.4150.2500.4151tQH - tDQSQ

140.615.6

075200

075200

0.61.10.6120,000

4020657520200.90.415

MAX

MIN

265/202

MAX

UNITSNOTES

tHP - tQHS

0.75120,000

nsnsnsnsnsnsnsns

1.10.6

tCKtCKnstCKns

0.6

tCKnstCK

22, 2331, 48

43

3838

0.2500.4151tQH - tDQSQ

140.615.6

18, 1917

nsµsµsnsnstCK

222121

tREFCtREFItVTDtXSNRtXSRD

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White Electronic DesignsNotes

1. All voltages referenced to VSS.2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be

conducted at nominal reference/supply voltage levels, but the related specifi cations and device operation are guaranteed for the full voltage range specifi ed.3. Outputs measured with equivalent load:

W3EG7218S-AD4

-BD4

PRELIMINARY

VTTOutput(VOUT)50ΩReference Point30pF4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test

environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifi cations are guaranteed for the specifi ed AC input levels under normal use conditions. The mini-mum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC).5. The AC and DC input level specifi cations are as defi ned in the SSTL_2 Standard

(i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level).

6. VREF is expected to equal VCCQ/2 of the transmitting device and to track variations

in the DC level of the same. Peak-to-peak noise (non-common mode) on Vref may not exceed ±2 percent of the DC value. Thus, from VCCQ/2, Vref is allowed ±25mV for DC error and an additional ±25mV for AC noise. This measurement is to be taken at the nearest VREF bypass capacitor.

7. VTT is not applied directly to the device. VTT is a system supply for signal

termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF.

8. IDD is dependent on output loading and cycle rates. Specifi ed values are obtained

with mini-mum cycle time at CL = 2 for -26A and -202, CL = 2.5 for -335 and -265 with the outputs open.

9. Enables on-chip refresh and address counters.10. IDD specifi cations are tested after the device is properly initialized, and is averaged

at the defi ned cycle rate.

11. This parameter is sampled. VCC = +2.5V ±0.2V, VCCQ = +2.5V ±0.2V, VREF = VSS, f

= 100 MHz, TA = 25°C, VOUT(DC) = VCCQ/2, VOUT (peak to peak) = 0.2V. DM input is grouped with I/O pins, refl ecting the fact that they are matched in loading.12. For slew rates < 1 V/ns and ≥ to 0.5 Vns. If the slew rate is < 0.5V/ns, timing

must be derated: tIS has an additional 50ps per each 100 mV/ns reduction in slew rate from 500 mV/ns, while tIH is unaffected. If the slew rate exceeds 4.5 V/ns, functionality is uncertain. For -335, slew rates must be 0.5 V/ns.

13. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at

which CK and CK# cross; the input reference level for signals other than CK/CK# is VREF.

14. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period

before VREF stabilizes, CKE < 0.3 x VCCQ is recognized as LOW.

15. The output timing reference level, as measured at the timing reference point

indicated in Note 3, is VTT.

16. tHZ and tLZ transitions occur in the same access time windows as data valid

transitions. These parameters are not referenced to a specifi c voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ).

17. The intent of the Don’t Care state after completion of the postamble is the DQS-driven signal should either be high, low, or high-Z and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions high [above VIHDC (MIN)] then it must not transition low (below VIHDC) prior to tDQSH (MIN).

18. This is not a device limit. The device will operate with a negative value, but system

performance could be degraded due to bus turnaround.

19. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE

command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS.20. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets

the minimum absolute value for the respective parameter. tRAS (MAX) for IDD

measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS.

21. The refresh period ms. This equates to an average refresh rate of 15.625µs

128MB. However, an AUTO REFRESH command must be asserted at least once every 140.6µs 128MB; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed.

22. The valid data window is derived by achieving other specifi cations: tHP (tCK/2), tDQSQ,

and tQH (tQH = tHP - tQHS). The data valid window derates in direct porportion with the clock duty cycle and a practical data valid window can be derived, as shown in Figure 7, Derating Data Valid Window. The clock is allowed a maximum duty cycle variation of 45/55, beyond which functionality is uncertain. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55.

23. Each byte lane has a corresponding DQS.

24. This limit is actually a nominal value and does not result in a fail value. CKE is

HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby).

25. To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through to the target AC

level, VIL(AC) or VIH(AC).

b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC

level, VIL(DC) or VIH(DC).26. JEDEC specifi es CK and CK# input slew rate must be ≤ 1V/ns (2V/ns

differentially).

27. DQ and DM input slew rates must not deviate from DQS by more than 10 percent.

If the DQ/ DM/DQS slew rate is less than 0.5 V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100 mv/ns reduction in slew rate. If slew rate exceeds 4 V/ns, functionality is uncertain. For -335, slew rates must be ≥ 0.5 V/ns.

28. VCC must not vary more than 4 percent if CKE is not active while any bank is active.29. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary

by the same amount.

30. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the device

CK and CK# inputs, collectively during bank active.

31. READs and WRITEs with auto precharge are not allowed to be issued until

tRAS(min) can be satisfi ed prior to the internal precharge command being issued.32. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or

2.9V, which ever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either - 300mV or 2.2V, whichever is more positive.

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White Electronic Designs33. Normal Output Drive Curves: a. The full variation in driver pull-down current from minimum to maximum process,

temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 8, Pull-Down Characteristics.

b. T he variation in driver pull-down current within nominal limits of voltage and

temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 8, Pull-Down Characteristics.

c. T he full variation in driver pull-up current from minimum to maximum process,

temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 9, Pull-Up Characteristics d. T he variation in driver pull-up current within nominal limits of voltage and

temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 9, Pull-Up Characteristics.

e. T he full variation in the ratio of the maximum to minimum pull-up and pull-down

current should be between 0.71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0V, and at the same voltage and temperature.

f. T he full variation in the ratio of the nominal pull-up to pull-down current should

be unity ±10 percent, for device drain-to-source voltages from 0.1V to 1.0V.34. The voltage levels used are derived from a mini-mum VCC level and the referenced

test load. In practice, the voltage levels obtained from a properly terminated bus will provide signifi cantly different voltage values.

35. VIH overshoot: VIH(MAX) = VCCQ + 1.5V for a pulse width !5 3ns and the pulse width

can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL(MIN) = -1.5V for a pulse width !5 3ns and the pulse width can not be greater than 1/3 of the cycle rate.36. VCC and VCCQ must track each other.

37. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will

prevail over tDQSCK (MIN) + tRPRE (MAX) condition.

W3EG7218S-AD4

-BD4

PRELIMINARY

c voltage level 38. tRPST end point and tRPRE begin point are not referenced to a specifi

but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE).39. During initialization, VCCQ, VTT, and VREF must be equal to or less than VCC + 0.3V.

Alternatively, VTT may be 1.35V maximum during power up, even if VCC/VCCQ are 0Vs, provided a minimum of 42 0 of series resistance is used between the VTT supply and the input pin.

40. The part operates below the slowest JEDEC operating frequency of 83 MHz. As

such, future die may not refl ect this option.

41. Random addressing changing and 50 percent of data changing at every transfer.42. Random addressing changing and 100 percent of data changing at every transfer.43. CKE must be active (high) during the entire time a refresh command is executed.

That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tREF later.44. IDD2N specifi es the DQ, DQS, and DM to be driven to a valid high or low logic level.

IDD2Q is similar to IDD2F except IDD2Q specifi es the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is “worst case.”

45. Whenever the operating frequency is altered, not including jitter, the DLL is required

to be reset. This is followed by 200 clock cycles.46. Leakage number refl ects the worst case leakage possible through the module pin,

not what each memory device contributes.47. When an input signal is HIGH or LOW, it is defi ned as a steady state logic HIGH or

LOW.

48. The -335 speed grade will operate with tRAS (MIN) = 40ns and tRAS (MAX) =

120,000ns at any slower frequency.

November 2004Rev. 1

10White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

元器件交易网www.cecb2b.com

White Electronic DesignsORDERING INFORMATION FOR AD4

Part NumberW3EG7218S262AD4W3EG7218S265AD4W3EG7218S202AD4

Speed

133MHz/266Mbps, CL=2133MHz/266Mbps, CL=2.5100MHz/200Mbps, CL=2

Height*35.05 (1.38\")35.05 (1.38\")35.05 (1.38\")

W3EG7218S-AD4

-BD4

PRELIMINARY

PACKAGE DIMENSIONS FOR AD4

2.0(0.079)67.56(2.66) MAX.3.81(0 .150) MAX.3.98 ± 0.1(0.157 ± 0.004)20(0.787)35.05(1.38) MAX.P12.31(0.091) REF.4.19(0.165)1.80(0.071)11.40(0.449)47.40(1.866)3.98(0.157) MIN.1.0 ± 0.1(0.039 ± 0.004)* All dimensions are in MILLIMETERS AND (INCHES)

November 2004Rev. 1

11White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

元器件交易网www.cecb2b.com

White Electronic DesignsORDERING INFORMATION FOR BD4

Part NumberW3EG7218S262BD4W3EG7218S265BD4W3EG7218S202BD4

Speed

133MHz/266Mbps, CL=2133MHz/266Mbps, CL=2.5100MHz/200Mbps, CL=2

Height*31.75 (1.25\")31.75 (1.25\")31.75 (1.25\")

W3EG7218S-AD4

-BD4

PRELIMINARY

PACKAGE DIMENSIONS FOR BD4

67.56(2.666) MAX3.81(0.150) MAX.3.98 ± 0.1(0.157 ± 0.004)20(0.787)31.75(1.25)2.31(0.091) REF.4.19(0.165)1.80(0.071)11.40(0.449)47.40(1.866)3.98(0.157) MIN.1.0 ± 0.1(0.039 ± 0.004)* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)

November 2004Rev. 1

12White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

元器件交易网www.cecb2b.com

White Electronic DesignsDocument Title

128MB – 16Mx72 DDR SDRAM UNBUFFERED w/PLL

W3EG7218S-AD4

-BD4

PRELIMINARY

Revision HistoryRev #

Rev ARev 0

History

Created

0.1 Data sheet spec updates

0.2 Changed datasheet from Advanced to Preliminary0.3 Added “BD4” package optionr

Release Date

7-23-039-04

Status

AdvancedPreliminary

Rev 11.1 Updated new IDD and CAP specs11-04Preliminary

November 2004

Rev. 1

13White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com